tag:blogger.com,1999:blog-40678464422473749532024-02-08T22:26:59.143+05:30My own technical guides for engineers!Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.comBlogger27125tag:blogger.com,1999:blog-4067846442247374953.post-90332802512924213922013-04-09T07:41:00.000+05:302013-04-09T07:41:00.492+05:30Closed loop gain of an amplifier<div dir="ltr" style="text-align: left;" trbidi="on">
In the following design pattern, V<sub>in</sub>, input voltage is applied to the non-inverting input terminal that means we get “Positive” value of amplifier’s output gain as compared to the "Inverting Amplifier" where we got the “Negative” value of output gain as per our pervious discussion.<br />
<br />
As an outcome of this, the input signal is “in-phase” with the output signal. By applying a minor portion of output voltage signal through voltage divider network Rf - R<sub>2</sub> to the inverting input i.e. by creating negative feedback, a feedback control system is accomplished.As illustrated the in figure, this closed-loop configuration generates a non-inverting amplifier circuit with very high input impedance, R<sub>in</sub> approaching infinity, low output impedance, R<sub>out</sub> ,very good stability as under ideally no current is flowing in the positive input terminal.<br /><br />
The same potential ( V<sub>1</sub> ) is applied at the intersection of feedback and input signal. That means at summing point junction is a "virtual earth". Resisters Rf and R<sub>2</sub> are used to develop a simple potential divider network in the non-inverting amplifier. As illustrated below the ratio of resisters Rf and R<sub>2</sub>, decides the output voltage gain of the circuit. Let’s calculate the Closed-loop voltage gain ( A V ) by applying the method to find out the output voltage of a potential divider network of Non-inverting Amplifier.<br />
<br />
<div style="text-align: center;">
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/1a8de57e6eb6c87e43ffec951a6069131.png" /></div>
<div style="text-align: center;">
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/2734f1e6f2ed28ec3547c055379334cc1.png" /><br />
<b> </b></div>
<div style="text-align: center;">
<b>Fig. Equivalent Potential Divider Network</b> <br /> </div>
<div style="text-align: center;">
For a Non-inverting Amplifier, closed loop voltage gain is given as:</div>
<div style="text-align: center;">
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/6d82154f25bf4fcd25f6a2fe35a687051.png" /><br />
For a Non-inverting Amplifier, closed loop voltage gain is a positive value which is always greater than unity (1) and is dependent on the ratio of Rf and R2. The gain of the amplifier will be right equal to unity (1) only if the Rf=0 i.e. value of the feedback resistor is zero. The gain of the amplifier will approaching infinity if the R<sub>2</sub>=0 . i.e. value of the feedback resistor is zero. If resistor R<sub>2</sub> is zero the gain will approach infinity, but usually it is restricted to the ( A<sub>o</sub> ), open-loop differential gain of an Op-Amp. If we change input connections as illustrated below then we can translate the system configuration from operational amplifier into a non-inverting amplifier. </div>
<div style="text-align: center;">
<br /></div>
<div style="text-align: center;">
<img alt="" height="145" src="http://www.faadooengineers.com/notes/images/3/2/cb5ab4ad38e4d7148997d1aa46cfb6201.png" width="225" /></div>
</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com1tag:blogger.com,1999:blog-4067846442247374953.post-13571672300611299842013-04-07T07:39:00.000+05:302013-04-07T07:39:00.612+05:30Nonlinearities in a system<div dir="ltr" style="text-align: left;" trbidi="on">
Homogeneity and superposition are the two properties of linear system. With superposition property we mean, output response of a system to the sum of inputs is the sum of the responses to the individual inputs. Therefore, if an input r<sub>1</sub>(t) gives an output for C<sub>1</sub> (t) and output for C<sub>2</sub>(r) is provided by r<sub>2</sub>(t) then with r<sub>1</sub>(t)- r<sub>2</sub>(t) as input, we will get C<sub>1</sub>(t) + C<sub>2</sub>(t) as output. The superposition property can be expressed as the system response with respect to product of input and scalar. Saying it in specific terms, for a linear system the homogeneity property can be concluded as if for an input of r<sub>1</sub>(i) that yields an output of c(t), an input of Ar<sub>1</sub>(t) yields an output of Ac<sub>1</sub>(t); that is, multiplication of an input by a scalar yields a response that is multiplied by the same scalar.
<br />
<br />
Linearity can be visualized with the help of Fig. 1. Figure 1(a) represents a linear system in which input is twice of the output or you can say that f(x) = 0.5x; without considering value of X. For instance, output will be ½ and 1 for input of 1 and 2 respectively. By using the superposition property, sum of the original inputs give inputs or 3 and it will give output as sum of original outputs means 1.5. For testing the property of homogeneity, we will take input as 2 and it will provide 1 as output value. Similarly multiplying the input by 2, also doubles the output. <br />
<br />
Figure 1(a) the input of 4 is not producing output of 2. In this way, the readers can check that linearity property is not verified here and is not applicable to the relationship depicted in the Fig. 1(b). Some useful examples of physical nonlinearities are shown in the Fig. 2. An Electronic Amplifier satisfies the property of linearity over specific range but at high value of input it exhibits non linearity known as saturation at high value of input voltages. A motor offers no response for low input value for voltage because of frictional forces which exhibits dead zone that is non linearity. Nonlinearity known as backlash is exhibited by gears which do not fit tightly. The input shifts only over a small range of values.<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/22bf27a69e473ac13ce7948becdcce571.png" /><br />
<b><u>FIGURE 1 a. Linear system; b. nonlinear system</u></b> <br />
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/1227fd9afabdc596c647e5c7013c63731.png" /><br />
<br />
<b><u>FIGURE 2 some physical nonlinearity</u></b><br />
Without responding of output, the readers are required to verify that the curves represented in the Figure 2. does not justify the linearity definitions over complete range. Phase Detector is one more example of nonlinear subsystem. It is used in the FM radio receiver as part of phase locked loop. The output response for input is sine of the input. Linear approximations can be made by the designer for a nonlinear system. Design and analysis are simplified with linear approximations. It can be used till good approximation to reality is yielded. For instance, if the range of input values about that point is small and translation of origin can be done to the point. Linear Amplification having little excursions about any point can be demonstrated by a physical device like electronic amplifiers.</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-12249417479826873722013-04-06T07:38:00.000+05:302013-04-06T07:38:00.768+05:30Time response of a dynamic system<div dir="ltr" style="text-align: left;" trbidi="on">
The information about how the system responds to certain inputs is provided by the time response of a dynamic system. To determine the stability of the system and the performance of the controller, we can analyze the time response. <br />
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Numerically integration of the system model in time is involved by obtaining the time response of a system. The time response of the control system can be found by finding its equation of motion and for that we need to model the overall system dynamics.<br />
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The system could be composed of the mechanical, electrical, or other sub-systems. In addition, each sub-system is expected to have sensors and actuators to sense the environment and to interact with it.<br />
In order to find the transfer function of all the sub-components and use the block diagram, we can use the Laplace transforms. We can use the signal flow diagrams in order to find the interactions among the system components.<br />
<br />
According to the objectives, the manipulation of the system final response by adding the feedback or poles and zeros to the system block diagram, can be done.
By using the inverse Laplace transforms, the overall transfer function of the system can be found and we can obtain the time response of the system to a test input normally a step input.<br />
<br />
The Lab VIEW Control Design and the Simulation Module provides Vis to help us to find these time-domain solutions.
To analyze the response of a system to step and impulse inputs, we can use this Time Response Vis.
Initial conditions can be applied to both of these responses.<br />
<br />
To simulate the response of the system to an arbitrary input, we can use the Time Response Vis.<br />
<br />
<b>Rise time (t<sub>r</sub>)</b> — It is the time required for the dynamic system response to rise from the lower threshold to an upper threshold. The default values are 10% for the lower threshold and90% for the upper threshold.<br />
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<b>Maximum overshoot (M<sub>p</sub>)</b>—the dynamic system response value that most exceeds the unity, expressed as a percent.<br />
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<b>Peak time (t<sub>p</sub>)</b> — it is the time required to reach the peak value of the first overshoot by the dynamic system response. <br />
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<b>Settling time (ts)</b> — it is the time required for the dynamic system response to reach and stay within a threshold of the final value. The default threshold is 1%.<br />
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<b>Steady state gain</b>— it is the final value around which the dynamic system response settles to a step input.<br />
<br />
<b>Peak value (y<sub>p</sub>)</b> — it is the value at which the maximum absolute value of the time response occurs.</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-48873977163896660142013-04-04T07:36:00.000+05:302013-04-04T07:36:00.194+05:30Routh Table - Entire row ZERO!<div dir="ltr" style="text-align: left;" trbidi="on">
<b>Entire row is zero</b><br />
<ul>
<li>If sometimes making a Routh table we find an entire row having zero as there is an even polynomial that is factor of original polynomial.</li>
<li>It is a different case from the case of zero in first column only. We will see an example how to construct and interpret the Routh table when an entire row is zero.</li>
<li>Further if the entire row is zero is appeared in Routh table when a purely even or purely odd polynomial is a factor of the original polynomial. Example s4 + 5s2 + 7 are an even polynomial as it has only powers of s.</li>
<li>Even polynomial only have roots that are in symmetry to the origin. Three conditions can occur .a) roots are symmetrical and real, b)roots are quadrantal, c)roots are symmetric and imaginary.</li>
<li>Figure 6.5 shows these cases. Each of the cases will generate even polynomial. It is an even polynomial that causes the row of zeros.</li>
</ul>
<ul type="disc">
<li>The row of zeros shows the existence of an even polynomial which has roots that are symmetric about the origin. Some of these roots can be on the j?-axis.</li>
<li>Now however the j? roots are symmetric about the origin, if there are no rows of zeros, we cannot have j? roots.</li>
<li>Another feature of Routh table is the row previous to the row that of the zero row has an even polynomial which is the factor of the original polynomial.</li>
</ul>
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/0e25a47828e1ecf65e9dc56cceaa86c71.png" /></div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-28921751467717591502013-04-03T07:52:00.002+05:302013-04-03T07:52:36.167+05:30Transient Response, Steady-State Response and Stability <div dir="ltr" style="text-align: left;" trbidi="on">
<b>1. </b><strong>Transient Response</strong><br /><br />
Transient response has a very important role in the system. For example if we apply it to the elevator we can see that with a slow transient response passengers will become impatient whereas when it is very rapid then it can be present very unpleasant and scary situation for them. A confusing situation may occur in case of elevator's oscillations just before the arrival of the floor. Some major structural changes can also occur with the transient response: a very fast transient response can result in permanent physical damage. Transient response also contributes for the time that is required for a computer to write to or to read from the computer's disk storage. As we know that it is not possible to read and write until head stops , hence head's read/write movement affects the computer's overall speed. With the help of this book, we will try to establish the quantitative definitions of the transient response. So that we can analyze the existing transient response of a system. Our primary Analysis and design objective is to get a preferred transient response and for that we can make the adjustments in the design components or parameters.<br />
<br />
<strong>2. Steady-State Response</strong><br />
<strong><br /></strong>
The Steady state response is the another goal of the analysis and design. This response seems like input and is something that remains when the transients are decayed to zero. For instance, this is a response seen when the elevator has stopped very close to the fourth floor or when the disk drive's head has stopped moving after the right track. The accuracy of the steady state response is a major concern for us.<br />
<br />For a comfortable exit of passengers it is important that an elevator should stop at a proper level with the floor. When the write or read tack is not placed over the command track then there are chances of getting computer errors. An antenna tracking of a satellite is done in order to maintain the satellite in its beam width so that it don't lose the track. In the text we will define the steady state errors on quantative basis, try to analyze the steady state error of the system and then corrective action are designed to decrease steady state error. This is our second analysis and design objective. <br />
And objective of design.<br />
<br />
<strong>3. Stability</strong> <br /><br />Without the stability, the discussion made in steady state error and on the transient response is doubtful. To give details about the stability we shall begin with the information that the sum of the forced response and the natural response makes up the system's total response.at the time of studying the linear differential equation, many of you may have referred to such responses as the homogeneous and particular solutions, respectively. The method by which a system acquires and dissipates energy was described by the natural response. The system and not the input is the factor that determines the response's nature or form. Whereas the input is responsible for the nature or form of the forced response. So to describe a linear system we can use: <br />
Total response = Natural response + Forced response (1.1)<sup>2</sup><br />
<br />
In order to make a control system useful, it is necessary for the natural response to reach zero, and so only the forced response should be left. However there are some cases where the natural response without any bound grows and rather than diminish to zero oscillate. Hence the natural response is so much higher to the forced response that it cannot be controlled and the situation is known as instability. Ultimately, this type of condition can end up with self destruction of the physical device until the device has no limit stops as its part. For instance, there are chances of an elevator to crash down through the ceiling or the floor, an aircraft can take uncontrollable roll, there are chances that the antennae that is supposed to point to the target can rotate, it may line up with the target and then can start oscillating for about the target with the increasing oscillations and velocity they can reach to an output limit till antenna are structurally damaged. One can also see this transient response in an unstable system which increases without any proof of steady state response.<br />
<br />
It is very important to design a control system to achieve stability. This can be achieved only when the natural response will decay up to the zero level when the time reaches the infinity or oscillate. In most of the systems we will find that the transient response and the natural response are directly proportional to each other. So, when the natural response degrades with the time approaching to infinity, transient response is going to die out, and only the forced response is left behind. When the system is stable then proper designing of steady state characteristics and transient response can be done. The third objective of analysis and design is stability. </div>
Anonymoushttp://www.blogger.com/profile/13510343234396107987noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-43435179044592045182013-04-03T07:51:00.001+05:302013-04-03T07:51:07.284+05:30Performance measurement of a control system<div dir="ltr" style="text-align: left;" trbidi="on">
The time domain characteristics are used to measure the control system' performance in a more realistic way. And the explanation for this is that most control system's performance is assessed on the basis of the time responses because of certain test signals. This is in distinction to the Communication system's analysis and design in which the frequency response is more important, as the maximum of the signals need to be processed are either composed of sinusoidal components or sinusoidal. In case of design problems, no unified methods of arriving at a designed system are there that fulfills the time-domain performance specifications, like rise time, maximum overshoot, settling time, delay time, and many more. Other than this, in the frequency domain, the graphical method's wealth is available that are not restricted to the low-order systems. <br />
<br />
It is necessary to understand that the time-domain performances and the frequency-domain are interconnected with each other in a linear system, hence the predictions on the system's time-domain properties can be done depending on the on the frequency-domain characteristics. The domain of frequency is very convenient for measuring the sensitivity of a system to parameter variations and noise. Having such concepts, we think that convenience and the availability of the existing analytical tools are main motivations for conducting control systems analysis and design in the frequency domain. Another reason is that it has given a second point of view to the problems of control-system, which usually gives important information in the control system's complex analysis and design. So, to conduct the linear control system's frequency-domain analysis does not mean that the system is only sinusoidal input's subject.<br />
<br />
With the help of the frequency-response studies,we can project the system's time-domain performance. the system's schematic and demonstrated this step for a position control system. In order to get a schematic, the engineers of control system have to make many simplifying assumptions so as to keep the ensuing model manageable and also can approximate the physical reality. The other step is to make the mathematical models from the schematics of physical systems. Here we will be discussing two methods: (1) transfer functions in the frequency domain and (2) state equations in the time domain.<br />
<br />
As we move further, we will see that the first step in every case for developing a mathematical model is the use of the fundamental physical laws of science and engineering. For instance, when electrical networks are modeled, Kirchhoff's laws and ohm's law, which are the important basic electronic network's laws should be applied first. We will add voltages in a loop or will sum the currents at a node. At the time of studying the mechanical systems, we have to use Newton's laws as the fundamental guiding principles. Here we will add up all the torques and forces. With all these equations we will get the relationship between the input and output of the system.<br />
<br />
The structure of the differential equation with its coefficients are the description of the system. Even though with the use of the differential equation the relation between the system's input and output can be made but, it is an unsatisfying representation with a system's perception. We can see that the parameters of system, like the coefficient, the inputs,r(t) and the output,c(t), are seen throughout the equation. It is better to go for the mathematical representation like in Figure 2.1(a), where the system, output and the input are the separate and distinct parts. Also we can represent easily the connection between many subsystems.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="http://www.faadooengineers.com/notes/images/3/2/5b5fd1ff95cad36fd7a4a92afaed4dfc1.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img alt="" border="0" src="http://www.faadooengineers.com/notes/images/3/2/5b5fd1ff95cad36fd7a4a92afaed4dfc1.png" /></a></div>
<br />
Like, we can show <em>cascaded</em><em> </em>interconnections, as shown in Figure <em>2.1(b), where there will be a mathematical function, known as the transfer function, is within each block and the block functions can be combined to get </em>Figure 2.1 <em>(a)</em><em> </em>for analysis and design. This convenience cannot be obtained with the differential equation.
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<div style="text-align: center;">
</div>
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Anonymoushttp://www.blogger.com/profile/13510343234396107987noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-31198718267214587172013-04-03T07:33:00.003+05:302013-04-03T07:33:35.280+05:30 Steady-State Error for Unity Feedback Systems <div dir="ltr" style="text-align: left;" trbidi="on">
Consider the following unity feedback system <br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/eb7c742d584ea72665228cd236ffbdd81.png" /><br />
Recall the closed-loop transfer function of the system, T(s), is<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/299eb9da7dfebad95550099dc70bc9701.png" /><br />
<br />
The system output can then be expressed as<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/d08be85908e4dcc375354830294830f41.png" /><br />
<br />
The error, E(s), between the system input, R(s), and the system output, C(s), is <br />
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/9ce49a1060caae731c4f0e3e56896be01.png" /><br />
<br />
Using the final value theorem, the steady-state error is<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/3/2/bb297ece4d3ec4d279dec9216a13a8a11.png" /></div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-31935013983938871672013-04-02T17:54:00.000+05:302013-04-02T17:54:00.541+05:30Current Transport Process in PN Junction<b>Introduction:</b> The current transport in contacts of metal-semi conductor is mainly due to majority carriers, in comparison to p-n junctions where minority carriers are responsible.<br />
<br />
<br />
<b>Current Transport Processes:</b> Figure provides below demonstrates five basic processes under forward bias (the inverse processes occur under reverse bias).<br />
These five processes are <br />
(1 )Electrons emission from the semi conductor over the potential barrier in the metal( the dominant process for Schottky diodes with moderately doped semiconductors (e.g., Si with N<sub>D</sub> < 10<sup>17</sup>cm<sup>-3</sup>) operated at moderate temperatures (e.g., 300 K)],<br />
(2) Quantum mechanical electrons tunneling through the barriers (crucial from heavily doped semiconductors and is accountable for most ohmic contacts) <br />
(3) recombination in the space-cahreg region( similar to the process of recombination in a p-n junction)<br />
(4) electron diffusion in the depletion region, and<br />
(5) holes injected from the metal which diffuse into the semiconductor which is similar to the recombination in the neutral region). <br />
<br />
Apart from this, we also have edge leakage current because of high electric field at the metal-contact interface or periphery current due to traps at the interface of metal semiconductor. Several methods are used for enhancing the quality of interface and various device structures have been proposed to minimize or remove the edge leakage current.<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/35e79e8c9e54e2cc1fb07cdb25612b871.png" height="263" width="567" /><br />
<br />
For typical high-mobility semiconductors (eg. Si and GaAs) the transport can be described adequately with the help of this theory of thermionic-emission. <br />
<br />
We will also consider the theory of diffusion which is applicable to low-mobility semiconductors and a generalized thermionic-emission-diffusion theory which is actually the synthesis of the two theories discussed earlier.<br />
<br />
The behavior of Schottky diode is electrically similar to single-sided abrupt p-n junction to some extent, and yet we can operate the Schottky diode as a majority-carrier device having inherent quick response.<br />
<br />
Therefore, the terminal functions of a p-n junction in general can be performed with the help of a Schottky diode with single exception as charge storage diode.<br />
<br />
This is because the time of charge storage in majority-carrier device is very small.<br />
<br />
One more difference is the greater density of current in a Schottky diode because of small built-in-potential with nature of thermionic emission in comparison to diffusion. It results in a quite smaller forward voltage drop.<br />
<br />
With same token, the demerit is the lower breakdown voltage and larger reverse current in the Schottky diode.Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-38164035266564006442013-03-31T17:53:00.000+05:302013-03-31T17:53:00.354+05:30Rectifying Contacts - Derivation
<b>Introduction:</b> This section gives brief explanation about the rectifying contacts with derivation:<br />
<b><br />
Rectifying Contacts:</b><br />
<ul>
<li>When we apply a forward bias voltage V to the Schottky barrier shown in fig. b, the contact potential is decreased from V<sub>0</sub> to V<sub>0</sub>-V(fig. a).</li>
<li>As a result, electrons in the semi conduction band can diffuse across the depletion region to the metal.</li>
<li>This help in producing the forward current (metal to semiconductor) through the junction.</li>
</ul>
<ul disc="" type="">
<li>Conversely, the barrier is increased to V<sub>0</sub> +V<sub>r</sub> by the reverse bias, and there is negligible flow of electron from semiconductor to metal. </li>
<li>In any of the case, electron flow from the metal to the semiconductor is slow down by the barrier F<sub>m</sub> - x.</li>
<li> The resultant equation of diode is equivalent to that of p-n junction. </li>
</ul>
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/681f50f10c76ef07a269fc31d5df88a91.png" height="33" width="143" /><br />
as suggested by figure c. Here, the reverse saturation current I<sub>0</sub> is not derived simply as it was done in the case of p-n junction.<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/451257cee44d22480c7903be153bd9621.png" height="450" width="604" /><br />
<ul>
<li>One crucial feature which can be predicted intuitively, however, is that the saturation current should be dependent on the barrier size F<sub>B</sub> for injection of electron from the metal in the semiconductors.</li>
</ul>
<ul disc="" type="">
<li>This barrier (for ideal case it is F<sub>m</sub> - x as represented in fig.) is not affected by the bias voltage. </li>
</ul>
<ul>
<li>We expect that we can find the probability of an electron which is surmounting this barrier with the help of Boltzmann factor. Therefore,</li>
</ul>
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/2bc715e12dbb1bd46c30dbc6fa99cf9a1.png" height="30" width="122" /><br />
<ul>
<li>In both cases, the Schottky barrier diode is rectifying, with small current in the reverse direction and easy flow of current in the forward direction. </li>
<li>It is also noted that in each case the forward current is due to majority carriers injection from the semiconductor in the metal.</li>
<li>The absence of injection of minority carriers and the related delay in storage is a notable feature of Schottky barrier diodes.</li>
</ul>
<ul disc="" type="">
<li>However some minority carrier injections occurring at high levels of current, these are essentially majority carrier devices. </li>
<li>Their switching speed and properties related to high-frequency are thus better than usual p-n junctions generally. </li>
</ul>
Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-31629124185018012312013-03-30T17:56:00.000+05:302013-03-30T17:56:49.117+05:30Depletion Capacitance - an introduction
<b>Introduction:</b> Mainly, there are two types of capacitance related with a junction:<br />
<ol>
<li>The capacitance of junction because of the dipole in the transition region.</li>
<li>The charge storage capacitance rising from the lagging behind of voltage as the current changes with the effects of charge storage. </li>
</ol>
<b>Depletion Capacitance:</b><br />
<br />
The junction capacitance is overriding under the conditions of reverse-bias and the charge storage capacitance is overriding if the junction is forward biased. In several applications of p-n junctions, for usefulness of the device the capacitance is a limiting factor. In place of the common expression C=Q/V, which is implemented on capacitors where charge is linear function of voltage, we should use the definition which is more general<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/9e5ff33a1464f776a4d11a08b9d0c4d51.png" height="60" width="98" /><br />
<br />
As the charge Q varies on each side of the transition region in non linear manner, <br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/206c1aee506206777eafc4774872e84e1.png" height="46" width="304" /><br />
we should use the changed value of the electrostatic potential barrier (V0 – V). Then, the right expression for transition region's width is <br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/2a277d52ccbfbe38332d8dc29929514d1.png" height="65" width="351" /><br />
<br />
We can write value of Q in terms of width of transition region and the concentration of doping on each side of the junction. <br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/224470185ce0fc505d6352bc6b0a19771.png" height="34" width="183" /><br />
<br />
Connecting the total width of the transition region W to the individual widths x<sub>p0</sub> and x<sub>n0</sub><br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/404ea40a5dd7fa4eaa6932b3a6fda9641.png" height="73" width="271" /><br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/19c3005fda7bbf348e9fa926d141656a1.png" height="135" width="431" /><img alt="" src="http://www.faadooengineers.com/notes/images/2/99/5b8e2765120bfc0c392dd2cf84a29d7d1.png" height="195" width="307" /><br />
<br />
and thus the charge on dipole's each side is <br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/a4b096b761248cec2338ad893e60aff41.png" height="51" width="344" /><br />
<br />
After that the junction capacitance C<sub>j</sub> can be written as <br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/99/e6b36c1662d7d24a10246ae9135dd4611.png" height="60" width="293" /><br />
Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-72634072209686736792013-03-30T17:52:00.000+05:302013-03-30T17:52:04.140+05:30Determination of Schottky-barrier with the help of measuring the activation energyThe main benefit of determination of Schottky-barrier with the help of measuring the activation energy is that we do not need any assumption of electrically active area. Particularly, this feature is crucial in the investigation of unusual or novel metal-semiconductor interfaces as we are not aware of the true value of the contacting area.<br />
<b><br />
Activation-Energy Measurement:</b><br />
<br />
If the surfaces are incompletely reacted or cleaned poorly then there will be only a little fraction of the geometric area in the electrically area. On the other side, a strong metallurgical reaction could provide rough nonplanar interface of metal-semiconductor with an electrically active area which is greater than the obvious geometric area.<br />
<br />
The electrically active area, we get<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/4752dc36f28b5430320e94998bd6e27e1.png" /><br />
where <img alt="" src="http://www.faadooengineers.com/notes/images/2/129/71cde084fbb94d8918feddfdcef9d05d1.png" height="23" width="86" /> is believed to be activation energy. For a limited temperature around the room temperature, the value of A** and F<sub>bn</sub> are necessarily independent of temperature.<br />
<br />
Therefore, for a fixed forward bias V<sub>F</sub> the slope of a plot of In(I<sub>F</sub>/T<sup>2</sup>) versus 1/T provides the barrier height F<sub>bn</sub> and the ordinate intercept at 1/T = 0 gives the multiplicative result<br />
of the electrically active area A and the effective Richardson constant A**.<br />
<br />
To show the importance of the method of activation-energy in the investigation of interfacial metallurgical reactions, Fig. provided below gives the plots of activation-energy of the saturation current in Al-n-Si contracts of different heights of barrier, easily formed by annealing at different temperature.<br />
<br />
The slopes of the plots depict an almost linear increase of effective Schottky barrier height from 0.71 to 0.81 V for annealing temperature between range of 450o C and 650o C.<br />
The C-V and I-V measurements also provide confirmation for these observations. <br />
Also, supposedly when the Al-Si eutectic temperature (= 580°C) is achieved, the genuine metallurgical nature of the interface of metal-semiconductor must be modified considerably.<br />
Determining the ordinary intercepts from the plots represented in the fig. show that the electrically active area enhances by factor of two, when the temperature of annealing exceeds the temperature of Al-Si eutectic-temperature.<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/5dcf2788c6d677a90fb3baac7bb8dea91.png" height="462" width="521" /><br />
Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-9384301113860567632013-03-26T07:35:00.000+05:302013-03-26T07:35:00.329+05:30Schmitt Trigger - Detailed explanation<div dir="ltr" style="text-align: left;" trbidi="on">
<br />
<div style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;">
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/ac2610b5173d5f24bf6d2ffb2cf7156f1.png" src="http://www.faadooengineers.com/notes/images/2/92/ac2610b5173d5f24bf6d2ffb2cf7156f1.png" /></div>
<br />
<b>Introduction: </b>The section below is the explanation for the Schmitt Trigger.<br />
<b><br />
Schmitt Trigger:</b><br />
<ul type="disc">
<li>If there is any sort of noise as an input to the comparator, the output can be in the erractive situation when v<sub>in</sub> is closer to the trip point.</li>
<li>For case in point, with parallel to a zero crossing, there is the lowest output wherein v<sub>in</sub> is in positive range and highest in case of negative v<sub>in</sub>.</li>
<li>Other than this, if the input consists of a noise voltage along with the peak of greater or equal to 1mV, then in such a case the comparator will notice the zero crossing developed by noise. </li>
<li> Fig 1.1 displays the zero crossing output discovery if there is noise in the input. </li>
</ul>
This can be kept away from by making use of a Schmitt trigger, the circuit that is on the whole a comparator having a positive feedback. Fig 1.2, depicts the reciprocal inverting Schmitt trigger circuit with OPAMP.<ul type="disc">
<li>With a reason of voltage divider circuit, it consist the positive feedback voltage.</li>
<li>In a situation wherein OPAMP is saturated positive, then in such a case, a positive voltage is the resultant feedback to the input that is non-inverting input, holding the output in the higher stage. (v<sub>in</sub>< v<sub>f</sub>).</li>
<li>With the negatively saturated output voltage, a feedback that is negative voltage to the case inverting input, investing the output in the lower state. </li>
<li>Next the output being +V<sub>sat</sub>, then here the reference voltage V<sub>ref</sub> is known by</li>
</ul>
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/f6ff5399fe6cd60deca0198b25dd24ad1.png" src="http://www.faadooengineers.com/notes/images/2/92/f6ff5399fe6cd60deca0198b25dd24ad1.png" /><br />
<ul type="disc">
<li>If V<sub>in</sub> is counted lesser in comparison to V<sub>ref</sub> then the output will continue to be +V<sub>sat</sub>.</li>
</ul>
<ul type="disc">
<li>When input v<sub>in</sub> hands to greater than V<sub>ref</sub> = +V<sub>sat</sub> the output, it switches from +V<sub>sat</sub> to –V<sub>sat</sub>. Here the reference voltage shall be given by</li>
</ul>
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/238dcc559cc62e637f96230eb0490cab1.png" src="http://www.faadooengineers.com/notes/images/2/92/238dcc559cc62e637f96230eb0490cab1.png" /><br />
<ul type="disc">
<li>The output will continue to be –V<sub>sat</sub> as long as v<sub>in</sub> > V<sub>ref</sub>.</li>
</ul>
<table border="0" cellpadding="0" cellspacing="0" style="width: 100%px;">
<tbody>
<tr>
<td style="width: 48.0%;"><div align="center">
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/6f8fd13d8afe0082054506a759211ca71.png" src="http://www.faadooengineers.com/notes/images/2/92/6f8fd13d8afe0082054506a759211ca71.png" /></div>
</td>
<td style="width: 52.0%;"><div align="center">
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/6f1bc908a92ceee580238f7439b7d9c71.png" src="http://www.faadooengineers.com/notes/images/2/92/6f1bc908a92ceee580238f7439b7d9c71.png" /></div>
</td>
</tr>
<tr>
<td><div align="center">
<b>Fig.1.3</b></div>
</td>
<td><div align="center">
<b>Fig. 1.4</b></div>
</td>
</tr>
</tbody>
</table>
</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-64340733051749634352013-03-25T07:24:00.000+05:302013-03-25T07:24:00.988+05:30Non-inverting Schmitt trigger - An introduction<div dir="ltr" style="text-align: left;" trbidi="on">
<b>Introduction: </b>The section below is the detailed explanation of the Non-inverting Schmitt Trigger. <br />
<b><br />
Non-inverting Schmitt trigger:</b><br />
<ul type="disc">
<li>In the case hereby, feedback is provided at the non-inverting terminal.</li>
<li>The inverting terminal is here grounded and along with this, the input voltage is apparently connected to the non-inverting input. fig1. 1, depicts a non-inverting Schmitt trigger circuit.</li>
</ul>
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/aabfb20abcb482c33026349763fb3d1a1.png" src="http://www.faadooengineers.com/notes/images/2/92/aabfb20abcb482c33026349763fb3d1a1.png" /><br />
<b>Fig. 1.1</b><br />
<ul type="disc">
<li>For the circuit behavior analysis, lets make an assumption that the produced output is saturated negative. </li>
<li>Then the feedback voltage is also negative (-V<sub>sat</sub>). Then the feedback voltage is also negative.</li>
<li>This feedback voltage will hold the output in negative saturation until the input voltage becomes +ve as much as required to result into making voltage positive. </li>
</ul>
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/e7e80d2729784f9c7408736181a8a72b1.png" src="http://www.faadooengineers.com/notes/images/2/92/e7e80d2729784f9c7408736181a8a72b1.png" /><br />
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/4dfd2b730f6392a5143f56ce591c35e61.png" src="http://www.faadooengineers.com/notes/images/2/92/4dfd2b730f6392a5143f56ce591c35e61.png" /><br />
<ul type="disc">
<li>When v<sub>in</sub> turns to be positive and eventhe magnitude is higher than than (R<sub>2</sub> / R<sub>1</sub>) V<sub>sat</sub>, then in such a case, the output turns to +V<sub>sat</sub>.</li>
<li> Therefore, the UTP at which the output switches to +V<sub>sat</sub>, is given by</li>
</ul>
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/ad0b1531bacb2b476192751699905f001.png" src="http://www.faadooengineers.com/notes/images/2/92/ad0b1531bacb2b476192751699905f001.png" /><br />
<ul type="disc">
<li>Similarly in the case wherein the output is at the saturation that is positive, feedback voltage is definitely positive.</li>
<li>To turn out to the output states, then input voltage has become negative enough to make.</li>
<li>When it happens, the output amends to the negative state from positive saturation to negative saturation voltage negative.</li>
</ul>
</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com2tag:blogger.com,1999:blog-4067846442247374953.post-84527785131669874962013-03-24T07:22:00.000+05:302013-03-24T07:22:00.874+05:30Relaxation Oscillator<div dir="ltr" style="text-align: left;" trbidi="on">
<b>Introduction: </b>The following explains the form by which the rectangle shape waves are attained with the support of Relaxation Oscillator. <br />
<br />
<b>Relaxation Oscillator:</b><br />
<br />
• With affirmative feedback it becomes possible to develop relaxation oscillator that leads to formation of rectangular wave.<br />
• The circuit is shown in fig1.1<br />
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/4ab8826e9fa47e5e7ee3c6b9b31991971.png" src="http://www.faadooengineers.com/notes/images/2/92/4ab8826e9fa47e5e7ee3c6b9b31991971.png" /><br />
<b>Fig. 1.1</b><br />
<br />
• In the circuit as above, a fraction R<sub>2</sub>/ (R<sub>1</sub> +R<sub>2</sub>) = b of the produced output is actually the feedback to the input terminal that is non-inverting.<br />
• The procedure of the circuit can be put in plain words as follows:<br />
• Assume that +V<sub>sat</sub> is the output voltage. The capacitor will charge exponentially toward +V<sub>sat</sub>.<br />
• The feedback voltage is +bV<sub>sat</sub>. When there is a rise in the capacitor voltage, the output +bV<sub>sat</sub> switches from +V<sub>sat</sub> to -V<sub>sat</sub>. <br />
• The feedback voltage becomes -V<sub>sat</sub> and the output will remain –V<sub>sat</sub>.<br />
• Thereafter the capacitor charges in the opposite direction. When the situation arises wherein the voltage decreases below –bV<sub>sat</sub> (more negative than –bV<sub>sat</sub>) , in that case, the output again turns up +V<sub>sat</sub>.<br />
• This process works in continuation and leads to the production of a square wave. Under stable state conditions, the capacitor voltage and output voltage are shown in fig1.1.<br />
• The incidence of the output can be obtained as follows:<br />
• The capacitor charges from -ß V<sub>sat</sub> to +ß V<sub>sat</sub> in the phase time period T/2. The capacitor charging voltage expression is given by 123.<br />
<br />
<br />
• In the frequency range of 10Hz to 10KHz, this square wave generator is immensely useful.<br />
• At elevated frequencies, the slew rate of the OPAMP confines the slope of the produced output square wave.</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-33173220534161241492013-03-23T07:20:00.002+05:302013-03-23T07:20:32.700+05:30Triangular Wave Generator<div dir="ltr" style="text-align: left;" trbidi="on">
<b>Introduction: </b>The following section that is given below is the complete explanation of the Triangular Wave generator.<br />
<br />
<b>Triangular Wave Generator:<br />
<br />
</b>• In the relaxation oscillator conferred in the preceding lecture, capacitor voltage V<sub>C</sub> has he shape of an approximately triangular wave but the sides of the triangles are exponentials instead of being a sharp straight line.<br />
• In order to make the triangle linear size, it is essential that C be concluded as the charge with a stable current rather that being the the exponential current through R.<br />
• The superior circuit is shown in Fig1.1<br />
<br />
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/0bdab195911dbe68e4ca0d1fe25b8e481.png" src="http://www.faadooengineers.com/notes/images/2/92/0bdab195911dbe68e4ca0d1fe25b8e481.png" /><br />
<br />
<b>Figure 1.1</b><br />
<br />
• In the given circuit an OPAMP Integrator is being used in order to supply a constant current to C in order to get a linear output.<br />
• Because of the inversion from the Integrator, the voltage is actually the fed back to the terminal that is non-inverting of the comparator instead of the inverting terminal. The rle of inverter is as a non-inverting Schmitt trigger.<br />
• The voltage v<sub>R</sub> is utilized to change the dc stage of the triangular wave and addition to this, voltage v<sub>s</sub> is utilized to alter the slopes of the waves that are triangular as shown in fig1.2<br />
<br />
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/d719366ab2435115fa6d68b1ce6222791.png" src="http://www.faadooengineers.com/notes/images/2/92/d719366ab2435115fa6d68b1ce6222791.png" /><br />
<b>Fig. 1.2</b><br />
• To get the result as maximum value in response of the triangular waveform presume that the square wave voltage v<sub>O</sub> is at its negative value = -V<sub>sat</sub>.<br />
• With a negative input, the output v (call) of the Integrator is actually the raising ramp. The voltage denoting at the non-inverting comparator input v<sub>1</sub> is expressed by</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-55818984452940730222013-03-23T07:18:00.001+05:302013-03-23T07:18:33.745+05:30Differnetial Amplifier - An introduction<div dir="ltr" style="text-align: left;" trbidi="on">
<b>Introduction:</b>
Differential amplifier is a basic building block of an op-amp. The main task of a differential amplifier is to amplify the difference between two input signals.<br />
<b><br />
Construction of Differential Amplifier:</b><br />
<ul>
<li>Let us consider two emitter-biased circuits as represented in fig. 1.1</li>
</ul>
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/e935d5c9604953954b77f2b8a01db9911.png" src="http://www.faadooengineers.com/notes/images/2/92/e935d5c9604953954b77f2b8a01db9911.png" /><br />
<b>Fig. 1.1 </b><br />
<ul>
<li>The characteristics of two transistors Q<sub>2</sub> and Q<sub>1</sub> are identical.</li>
</ul>
<ul type="disc">
<li>The circuits have equal resistances, that is R<sub>E1</sub> = R<sub>E2</sub>, R<sub>C1</sub> = R<sub>C2</sub> and the magnitude of –V<sub>EE</sub> and +V<sub>CC</sub> are equal. We can measure the voltages with respect to ground. </li>
<li>To make a differential amplifier, the two circuits are attached together as represented in fig. 1.1. The two +V<sub>EE</sub> and +V<sub>CC</sub> provides terminal are formed common because they are similar. </li>
<li>We exchange the parallel combination of R<sub>E1</sub> and R<sub>E2</sub> with resistance R<sub>E</sub> and the two emitters are connected also. </li>
<li>The two input signals v<sub>1</sub> & v<sub>2</sub> are applied at the base of Q<sub>1</sub> and at the base of Q<sub>2</sub>. The output voltage is taken between two collectors.</li>
<li>The resistances of the collectors are equal and thus denoted with the help of R<sub>C</sub> = R<sub>C1</sub> = R<sub>C2</sub>. </li>
<li>In ideal situation, the output voltage is zero when the two input values are equal. In case v<sub>1</sub> is more than v<sub>2</sub> then the output voltage with polarity shown appears. Also, if v<sub>1</sub> is more than v<sub>2</sub> then the polarity of output voltage is opposite. </li>
<li>The configurations of differential amplifiers are different. </li>
<li>The configurations of four differential amplifiers are provided as: </li>
</ul>
<ul>
<li>Dual input, unbalanced output differential amplifier.</li>
</ul>
<ol start="2" type="1">
<li>Dual input, balanced output differential amplifier.</li>
<li>Single input unbalanced output differential amplifier.</li>
<li>Single input balanced output differential amplifier.</li>
</ol>
</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-17505962362797381442013-03-23T07:16:00.002+05:302013-03-23T07:16:39.110+05:30Dual Input, Unbalanced Output Differential Amplifier<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
</div>
<div style="margin-left: 1em; margin-right: 1em;">
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/d6e880934acf32d103f27dab2cdb81ce1.png" height="215" src="http://www.faadooengineers.com/notes/images/2/92/d6e880934acf32d103f27dab2cdb81ce1.png" width="400" /></div>
<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
</div>
<div style="margin-left: 1em; margin-right: 1em;">
<img alt="" data-cke-saved-src="http://www.faadooengineers.com/notes/images/2/92/04e1e4b940aa41414c92ff18aba097391.png" height="225" src="http://www.faadooengineers.com/notes/images/2/92/04e1e4b940aa41414c92ff18aba097391.png" width="400" /></div>
<br />
<br />
<b></b><br />
<ul>
<li>These configurations are represented in fig 1.2 and are defined by the number of input signals used and the manner in which output voltage is calculated.</li>
<li>In case of two input signals, the configuration is known as dual input, otherwise it is a single input configuration.</li>
<li>On the other hand, in case the output voltage is determined between two voltages, it is known to as a balanced output because the dc potential of both the collectors are same with respect to ground, the configuration is known as unbalanced output.</li>
<li>A multistage amplifier having a required gain can be determined with the help of direct connection between successive stages of differential amplifiers.</li>
</ul>
<ul type="disc">
<li>The benefit of direct coupling is that the lower cut off frequency is removed which is imposed by the coupling capacitors, and thus they have the ability of amplifying both ac input signals and dc input signals.</li>
</ul>
</div>
Anonymoushttp://www.blogger.com/profile/00410821721580007614noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-82184000426608139192013-03-19T08:37:00.000+05:302013-03-19T08:37:00.648+05:30Basic digital-circuit building blocks of both logic and memory circuits<b>Introduction:</b> Herein this section, the basic digital-circuit building blocks of both logic and memory circuits are presented. The basic unit for a logic circuit is an inverter. Different configurations for MOSFET inverters.<br />
<b><br />
Basic Circuit Blocks:</b>
Most commonly used is CMOS (complementary MOS) inverter where both p-channel and n-channel transistors are used. This logic uses extremely low dc power as one of the transistors in series remains off whether the input is low or high and so very little steady-state current (sub-threshold current) passes through them.<br />
<br /> This is, in fact, one of the biggest advantages and applications of MOSFETs in which the insulated gate can tolerate input voltage of any polarity.
Such arrangement with bipolar transistors or MESFETs is quite difficult to maintain if a large resistor in not put in front of the input.<br />
<br /> In NMOS logic (shown in Fig. b), load of p-channel transistor is substituted with a depletion-mode n-channel transistor.
The clear advantage of using this simpler technology is that it does not require a p-channel device at the expense of higher dc power.<br />
<br />
This kind of a depletion-mode device with the gate tied to the source is a two-terminal non-linear resistor basically, which is an improvisationover a simpleresistor load that is shown in Fig. c.<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/1cd5ecb3f9935a6dad89407f36e0aa901.png" height="180" width="400" /><br />
<br />
<br /> Two elementary MOSFET memory cells, for DRAM (dynamic random-assess memory) and SRAM (static random-access memory) circuits, are illustrated in Fig. below.
There are two CMOS inverters connected back to back in a SRAM cell. It is a latch and a stable cell but it needs four transistors (six which includes controls for word line and bit line).<br />
<br />
The memory density of DRAM cell is very high as it just uses one transistor. The memory is stored as a charge across its capacitor. As there is finite charge leakage in the non-ideal capacitor, the cell requiresperiodic refreshing, typically at a frequency of 100 Hz.<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/44eda4db8e84a9811c1fb2221c09b8401.png" height="285" width="529" />Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-1879721182358344712013-03-18T08:35:00.000+05:302013-03-18T08:35:00.017+05:30Introduction to MOSFET<b>Introduction:</b> MOSFET is an ideal transconductance amplifier which has infinite input resistance and a current generator at the output. However, in practice, there are several other non-ideal circuit elements.<br />
<br />
<b>Equivalent Circuit and Microwave Performance:</b>
An equivalent circuit for common-source connectionis shown in Fig. given below.
The gate resistance R<sub>G</sub> is associated with the gate contact material over the oxide. <br />
<br />
The input resistance i.e. R<sub>in</sub> is an outcome of tunneling current through the thin gate insulator, and also includes conductance through defects.This is nothing but a function of oxide thickness.<br />
<br />
For a silicon dioxide layer i.e. thermally grown, the leakage current between gate and the channel is trivial; so the input resistance is very high, i.e. one of the main advantages of a MOSFET.<br />
<br />
For oxides below thickness of 5 nm, tunneling current becomes a significant factor.<br />
<div style="text-align: center;">
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/01bad1a758d9c910595cf312308725fe1.png" height="230" width="524" /></div>
In the saturation region, V<sub>D</sub> and thus R<sub>D</sub> has little effect on the drain saturation current. <br />
<br />
The R<sub>s</sub> affects effective gate bias, and the extrinsic transconductance is calculated with help of<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/bd0c738dafb35f84a6b4324748a91f051.png" height="53" width="153" />equation (1)<br />
<br />
When the microwave performance is analyzed, and the cutoff frequency fTi.e. defined as the frequency for unity current gain (i.e. the ratio of drain current to gate current) is attained,<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/e5850440ad866b0be553697d612c1f161.png" height="51" width="294" />equation (2)<br />
<br />
In ideal case where there is zero parasitics, it can be illustrated that<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/99e7316fbc8900b656114a793e7cfd5b1.png" height="77" width="137" />equation (3)<br />
<br />
For very large source and drain resistances, the comprehensive expression is given by<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/091b6effc9317553ec9a802b4beed3de1.png" height="65" width="339" />equation (4)<br />
<br />
The other figure-of-merit<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/0ad25782ec7f9b57536be7adc423225e1.png" height="64" width="152" />Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-59265904311042588962013-03-18T08:23:00.000+05:302013-03-18T08:23:00.420+05:30Schottky-Barrier Source/Drain MOSFET<br />
<b>Introduction:</b> In lieu of p-n junction, use of Schottky-barrier contacts for source and drain of a MOSFET can give some benefits in assembly and performance.<br />
<b><br />
Schottky-Barrier Source/Drain:</b>
Figure depicts a schematic MOSFET structure with such Schottky source and drain. For Schottky contact, junction depth can be effectively made zero to abate the short-channel effects.<br />
<br />
n-p-n bipolar-transistor action is also absent for undesirable effects such as bipolar breakdown and latch-up phenomenon in CMOS circuits.
Removing high-temperature implant anneal encourage better quality in oxides and better control over geometry.<br />
<br />
Additionally, this structure can be formed on semiconductors likeCdS where p-n junctions can’t be easily formed.<br />
<br />
<div style="text-align: center;">
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/d4d65f808ee3763391550f5b25ef1a8f1.png" height="402" width="416" /></div>
<br />
Figures b-d illustrates the working principle of Schottky source drain.
At thermal equilibrium with V<sub>G</sub> = V<sub>D</sub> = 0, metal’s barrier height to the p-substrate for holes is qF<sub>Bp</sub> (e.g., 0.84 eV for an ErSi-Si contact).<br />
<br />
When gate voltage is above threshold so as to invert the surface from p to n-type, barrier height between source and the inversion layer (electrons) is qF<sub>Bp</sub>= 0.28 eV.<br />
<br />
It is to be noted that source contact is reverse biased under operating conditions (shown in Fig. d).<br />
<br />
For a 0.28-eV barrier at room temperature, thermionic-type reverse-saturation current density is required to be of the order of 10<sup>3</sup> A/cm<sup>2</sup><br />
<br />
To accentuate current density, metals should be selected to yield highest majority-carrier barrier sothat minority-carrier barrier height is minimized.<br />
Surplus current arising due to tunneling through the barrier should help in improving the channel carriers supply.<br />
Currently, forming the structure on a p-type Si substrate for n-channel MOSFET is much moredifficult as compared to p-channel device with n-substrate, because silicidesand metals that yieldhuge barrier heights on p-type silicon are less common.<br />
The main drawbacks of Schottkysourceldrain are high series resistance due to higher drain leakage current and finite barrier height.Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-88012785090224858032013-03-17T22:34:00.000+05:302013-03-17T22:34:00.094+05:30Power MOSFETS - DMOS & LDMOS<b>Introduction:</b>
Generally, power MOSFETs having longer channel lengths employ deeper junctions and thicker oxides. This also posts a penalty on device performance like the transconductance (g<sub>m</sub>) and speed ( f<sub>T</sub>). Yet, power applications from MOSFETs are on a rise, thanks to requirement of very high voltage, for instance, by cellular phones and cellular base stations which are in high demand. <br />
<b><br />
DMOS: </b>As implied, in DMOS (double-diffbsed MOS) transistor illustrated in Fig. (a), the higher diffusion rate of p-dopant (e.g., boron) against the n<sup>+</sup>-dopant (e.g., phosphorus) of the source helps in determining the channel length. This technique is capable of producing very short channels and do not depend on lithographic mask.<br />
<br />
The p-diffusion has good punch-through control and serves as channel doping. A lightly doped n<sup>-</sup> - drift region follows this channel. This drift region is relatively long compared to the channel and also minimizes the highest electric field in this region by maintaining a uniform field. The drain is usually located at the substrate contact.<br />
<br />
The field near the drain is and the drift region is same and thus, avalanche breakdown, multiplication and oxide charging are diminishedin comparison to conventional MOSFETs. However, it is pretty much difficult to control the threshold voltage VT in a DMOS transistor as channel doping is not constant along its length.<br />
<br />
As VT is determined by local doping concentration along the surface of the semiconductor, varying doping level results in variations in VT as a function of bias and distance.<br />
Besides, the localization of punch-through control by a thin p-shield region requires a higher doping level in comparison to a conventional structure and it results in much poor turn-off behavior for DMOS transistors.<br />
<br />
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/bec34adf5b73b7fd162c64b6bc3a949d1.png" height="161" width="400" /><br />
<br />
<b> LDMOS:</b>
The main difference between LDMOS (laterally diffused MOS) transistor (shown in Fig. b) and a DMOS transistor is that it has a lateral current-flow pattern. Herein this, the drift region is an implanted horizontal region.<br />
<br />
This type of horizontal arrangement renders p<sup>+</sup>-substrate with the ability to deplete this drift region at high drain bias. Nevertheless, at low drain bias, it’s higher doping creates lower series resistance.<br />
Thus, the drift region behaves as a nonlinear resistor. At low drain bias, its resistance is determined using 1/nqµ. At high drain bias, this region is fdly depleted to support a large voltage drop.<br />
This concept is known as RESURF (reduced surface field) technology.<br />
<br />
Due to this feature, drift region can be doped with much higher concentration than DMOS transistor for a lower on-resistance. The other advantage of LDMOS transistor is that source can be internally tied to the substrate with help of deep p-type diffusion.This prevents the use of a bond wire with high inductance to the source.<br />
<br />
Thus, LDMOS transistor can perform at higher speed.Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com1tag:blogger.com,1999:blog-4067846442247374953.post-64822287628852629492013-03-17T12:27:00.000+05:302013-03-17T12:27:00.983+05:30Silicon on insulator & thin film transistor<b>Introduction:</b>
Herein this article, the SOI and thin-film transistor (TFT) will be described in the following way.<br />
<b><br />
SOI:</b>
In contrast to thin-film transistor, top silicon layer of an SOI (silicon-on-insulator) wafer is a premium-quality single-crystalline material i.e. apt for high-density and high-performance integrated<br />
Several forms of SOI structures have been demonstrated using different holding substrates and insulator materials.<br />
<br /> These consist of silicon-on-oxide, silicon-on-sapphire (SOS), silicon-on-zirconia (SOZ), and siliconon-nothing(air gap).
In SOZ and SOS technologies, upon a crystalline insulating substrate, single-crystalline silicon film is epitaxially grown. In these, insulators themselves serve as the substrates, ZrO<sub>2</sub> in SOZ and Al<sub>2</sub>O<sub>3</sub> in SOS.<br />
<br />
The difficultywith these techniques is that the material quality gets disturbed when the film gets thinner. The most popular is the one that was the first option and which used oxide as an insulator and another that used Si wafer as the holding substrate. There are several ways to construct this structure. One is where SIMOX (separation by oxygen implantation) is used and where high-dose oxygen is implanted onto a silicon wafer followed by annealing at high temeparture to create buried SiO<sub>2</sub> layer.<br />
<br />
In another technique, bonding of two silicon wafers is involved. One silicon wafer has an oxidized layer followed by thinning or completely removed majority of the top wafer until a thin silicon layer is left. In one technique, lateral epitaxial growth of silicon over an oxide layer is usedthat starts from a seed opening to the substrate.<br />
<br />
Another technique employs laser recrystallizationthat transforms amorphous silicon deposited on the oxide layer to single-crystalline material, or poly-crystalline form with large grain size. A schematic diagram of n-channel MOSFET made on an SOI substrate is shown in Figure (a) with its typical I-Vcharacteristics illustrated in Fig. (b). The kinks which are associated with floating body lacking a substrate tie are easily noticeable.
<br />
<div style="text-align: center;">
<img alt="" src="http://www.faadooengineers.com/notes/images/2/129/63c39e180054ed214aa48f03b102e3491.png" height="150" width="400" /></div>
<br />
<b>Thin-Film Transistor (TFT):</b> The thin-film transistor is usually referred to as MOSFET unlike other types of transistors. Their structure is same as MOSFET that is built on SOI except for that their active film is a deposited thin film while it may have any form of substrate.<br />
<br />
Since a semiconductor layer is formed by deposition, there are more defects and imperfections in amorphous material than single-crystalline semiconductors and that results in more complex transport processes in TFT. To improve the performance, reliability and reproducibility of a device, the bulk and interfacetrap densities must be diminished to reasonable levels.<br />
Due to lower mobility, current in a TFT is always quiterestricted and leakage current is always higher because of defects.<br />
<br />
Its main applications are in those areas where a flexible substrate or large-area is required and it is not feasible to carry out conventional semiconductor processing. Its fine example is a large-area display where an array of transistors in turn controlsan array of lighting elements.<br />
<br />
In such applications, device performance parameters such as speed or current are not critical.Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com1tag:blogger.com,1999:blog-4067846442247374953.post-26591396640353727132013-03-17T08:21:00.003+05:302013-03-17T08:21:51.496+05:30Source/Drain Design - Lightly doped drain<b>Introduction:</b> The extension close to the channel has shallower junction depth that minimizes short-channel effects. Sometimes, it is less heavily doped to diminish the lateral field for considering hot-carrier aging.<br />
<b><br />
Source/Drain Design:</b>
For this purpose, it is referred to as lightly doped drain (LDD). The deeper junction depth away from the channel helps in minimizing the series resistance.<br />
<br /> The gradient or sharpness of the source/drain profile is crucialfor minimizing series resistance as pointed out earlier. Fig. below serves as a reference to understand its origin.<br />
<br />
The profile is never perfectly abrupt practically, and there is a region of accumulation layer (of n-type) before current starts spreading in bulk of the source/drain. This accumulation-layer resistance R<sub>ac</sub> is associated with the transition distance prior to doping attaining a critical level.<br />
<img src="http://www.faadooengineers.com/notes/images/2/129/92a5cfafb1db08f532cb07fcaeeeed121.png" height="318" width="519" /><br />
<br /> The development of the silicide contact technology, which began in early 1990s, was a milestone for source/drain design. In contrast to metal contact, silicide can be made to self-align to the gate, therebydiminishing the sheet-resistance component (R<sub>sh</sub>) between contact and the channel.<br />
<br /> In this manner,silicide becomes the metal contact as the contact resistance between metal and silicide is very insignificant.
This self-aligned silicide process has been coined silicide which is described as follows.<br />
<br />
After the gate definition, an insulator spacer is created on the gate sides. A metal layer for silicidation is uniformlydeposited and at this stage shortens the gate and source/drain.
After thermal reaction occurs at low temperature (= 450°C), metal reacts with silicon on the sourceldrain regionto form silicide.<br />
<br /> Its formation on the gate is optional and it depends on whether the gate is capped or not with insulation layer i.e. a part of the gate stack.
Metal found over the spacer region and the field region (between transistors, i.e. not shown) remains as metal since no exposed silicon is available for reaction.<br />
<br /> Then, metal is removed with a selective chemical that only etches metal without etching silicide, thereby eliminating the shorting paths.
It is to be noted that silicide/silicon interface is somewhat recessed due to the intake of silicon during formation of silicide.<br />
<br />
Examples of salicidesare , Nisi<sub>2</sub>, CoSi<sub>2</sub>, TiSi<sub>2</sub>and PtSi.Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-53915948295254308502013-03-17T08:18:00.002+05:302013-03-17T08:19:42.836+05:30 Drain-Induced Barrier Lowering (DIBL)<b>Introduction:</b> It’s pointed out already that when source and drain depletion regions form a substantial fraction of channel length, short-channel effects begin to take place. In extreme cases when sum of these depletion widths will approach the channel length (y<sub>s</sub> +y<sub>D</sub> = L), effects will be more serious. This condition is commonly known as punch-through. Its net result is a large leakage current between source and drain and this current is a strong function of the drain bias.<br />
<br />
<b>Drain-Induced Barrier Lowering (DIBL):</b> <br />
<br />
The punch-through originates from the lowering of barrier close to the source, commonly called as DIBL (drain-induced barrier lowering).<br />
<br />
When drain is near the source, the drain bias is capable of influencing the barrier at the source end, such that channel carrier concentration at that location does not remain fixed.<br />
<br />
This occurrence is demonstrated by energy bands along the surface of the semiconductor, as shown in Fig. below.<br />
<br />
A drain bias can alter the effective channel length but the barrier at the source end remains constant for a long channel device. However, for a short-channel device, the same barrier is no longer fixed.<br />
When the source barrier is lowered, it causes an injection of extra carriers that increases the current significantly.<br />
<br />
This increase shows up in subthresholdand above-threshold regimes.<br />
<br />
<img src="http://www.faadooengineers.com/notes/images/2/129/0f66a084c0e7c9e0f6004e47c8c906d21.png" height="137" width="400" /><br />
<br />
It is shown in the Figure given above that punch-through condition is observed at the semiconductor surface. In practically used devices, substrate concentration is reduced below the depth of sourceldrain junction which broadens the depletion widths so that punch-through can also occur via a path in the bulk.<br />
<br />
The punch-through drain voltage can be assessedusing depletion approximation as<br />
<img src="http://www.faadooengineers.com/notes/images/2/129/f8c2d354d1628d5745eb83508f6e4aca1.png" height="69" width="206" />equation (1)<br />
<br />
The space-charge-limited currentwill dominate the drain current:<br />
<br />
<img src="http://www.faadooengineers.com/notes/images/2/129/ce047fdcab6d7d9365752f6bf789d3b71.png" height="51" width="138" />equation (2)<br />
<br />
where A is cross-sectional area of the punch-through path. The space-chargelimited current increases gradually with V<sub>D</sub><sup>2</sup> and is parallel to inversion-layer current.<br />
<br />
The calculated points as shown in the figure are obtained from a 2-dimensional computer calculation that incorporates the field-dependent mobility effect and punch-through effect.Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0tag:blogger.com,1999:blog-4067846442247374953.post-28626390880931758892013-03-17T08:15:00.000+05:302013-03-17T08:15:55.405+05:30Use of control systems in day-to-day lifeIt is easy to raise heavy things with the help of the control system. Without control system, one will find it exceedingly difficult practically.<b> </b>Huge antennas can be pointed towards farthest points of the universe so that faintest radio signal can be picked. Control of these antennas with the use of the hand is almost impossible.<br />
<br />
It is with the support of control systems; elevators can carry us at high speed to the desired destinations with automatic stopping at the correct floor.<b> </b>The power requirement for speed and load cannot be provided only by us only. It is the motors that support the power, the control systems monitor and regulate speed as well as position.<br />
<br />
Reasons for developing control systems are: <br />
<ul>
<li>Power amplification</li>
<li>Disturbances compensation</li>
<li>Input Form convenience </li>
<li>Power amplification</li>
</ul>
For example, The Radar Antenna needs a larger quantity of power or force to generate the output as rotation when sited by a low power rotary motion of a knob as its input.
The required power gain or power amplification can be formed by the control system. These are beneficial so as to overcome the difficulties of a functioning human.<br />
<br />
Control systems are beneficial in dangerous or remote locations like a remote controlled robotic arm to pick up the material is a better option in a radioactive environment.<b> </b>Control systems make the things convenient by varying the type of input. As in the case of temperature control system, the output heat is generated by the position on thermostat as input.<br />
<br />
Normally, such variables are controlled as per the temperature in the thermal systems whereas in mechanical systems, velocity and position and in electrical systems as current, voltage and frequency in the electrical systems.<br />
<br />
The system must provide the right output even in the situation wherein there is a disturbance of any kind. For example, take the system of antenna that points towards the commanded direction. <br />
<ul>
<li>The system should spot the disturbance and rectify the position of the antenna if the antenna is forced by the wind in contrast to the commanded direction or if any sort of noise comes internally. </li>
<li>There is no change or variation in input, in case of rectification or correction. </li>
<li>In the general case, the disturbance is measured by the system which has resulted in the repositioning of the antenna. Thereafter changes the direction of the antenna to a commanded position as per the input. </li>
</ul>
Anonymoushttp://www.blogger.com/profile/07282541237117351103noreply@blogger.com0