Basic digital-circuit building blocks of both logic and memory circuits

Introduction: Herein this section, the basic digital-circuit building blocks of both logic and memory circuits are presented. The basic unit for a logic circuit is an inverter. Different configurations for MOSFET inverters.

Basic Circuit Blocks:  Most commonly used is CMOS (complementary MOS) inverter where both p-channel and n-channel transistors are used. This logic uses extremely low dc power as one of the transistors in series remains off whether the input is low or high and so very little steady-state current (sub-threshold current) passes through them.

This is, in fact, one of the biggest advantages and applications of MOSFETs in which the insulated gate can tolerate input voltage of any polarity. Such arrangement with bipolar transistors or MESFETs is quite difficult to maintain if a large resistor in not put in front of the input.

In NMOS logic (shown in Fig. b), load of p-channel transistor is substituted with a depletion-mode n-channel transistor. The clear advantage of using this simpler technology is that it does not require a p-channel device at the expense of higher dc power.

This kind of a depletion-mode device with the gate tied to the source is a two-terminal non-linear resistor basically, which is an improvisationover a simpleresistor load that is shown in Fig. c.




Two elementary MOSFET memory cells, for DRAM (dynamic random-assess memory) and SRAM (static random-access memory) circuits, are illustrated in Fig. below. There are two CMOS inverters connected back to back in a SRAM cell. It is a latch and a stable cell but it needs four transistors (six which includes controls for word line and bit line).

The memory density of DRAM cell is very high as it just uses one transistor. The memory is stored as a charge across its capacitor. As there is finite charge leakage in the non-ideal capacitor, the cell requiresperiodic refreshing, typically at a frequency of 100 Hz.

Introduction to MOSFET

Introduction: MOSFET is an ideal transconductance amplifier which has infinite input resistance and a current generator at the output. However, in practice, there are several other non-ideal circuit elements.

Equivalent Circuit and Microwave Performance:  An equivalent circuit for common-source connectionis shown in Fig. given below. The gate resistance R_G is associated with the gate contact material over the oxide.

The input resistance i.e. R_in is an outcome of tunneling current through the thin gate insulator, and also includes conductance through defects.This is nothing but a function of oxide thickness.

For a silicon dioxide layer i.e. thermally grown, the leakage current between gate and the channel is trivial; so the input resistance is very high, i.e. one of the main advantages of a MOSFET.

For oxides below thickness of 5 nm, tunneling current becomes a significant factor.

In the saturation region, V_D and thus R_D has little effect on the drain saturation current.

The R_s affects effective gate bias, and the extrinsic transconductance is calculated with help of
equation (1)

When the microwave performance is analyzed, and the cutoff frequency fTi.e. defined as the frequency for unity current gain (i.e. the ratio of drain current to gate current) is attained,

equation (2)

In ideal case where there is zero parasitics, it can be illustrated that

equation (3)

For very large source and drain resistances, the comprehensive expression is  given by

equation (4)

The other figure-of-merit

Schottky-Barrier Source/Drain MOSFET

Introduction: In lieu of p-n junction, use of Schottky-barrier contacts for source and drain of a MOSFET can give some benefits in assembly and performance.

Schottky-Barrier Source/Drain:  Figure depicts a schematic MOSFET structure with such Schottky source and drain. For Schottky contact, junction depth can be effectively made zero to abate the short-channel effects.

n-p-n bipolar-transistor action is also absent for undesirable effects such as bipolar breakdown and latch-up phenomenon in CMOS circuits. Removing high-temperature implant anneal encourage better quality in oxides and better control over geometry.

Additionally, this structure can be formed on semiconductors likeCdS where p-n junctions can’t be easily formed.

Figures b-d illustrates the working principle of Schottky source drain. At thermal equilibrium with V_G = V_D = 0, metal’s barrier height to the p-substrate for holes is qF_Bp (e.g., 0.84 eV for an ErSi-Si contact).

When gate voltage is above threshold so as to invert the surface from p to n-type, barrier height between source and the inversion layer (electrons) is qF_Bp= 0.28 eV.

It is to be noted that source contact is reverse biased under operating conditions (shown in Fig. d).

For a 0.28-eV barrier at room temperature, thermionic-type reverse-saturation current density is required to be of the order of 10³ A/cm²

To accentuate current density, metals should be selected to yield highest majority-carrier barrier sothat minority-carrier barrier height is minimized.
Surplus current arising due to tunneling through the barrier should help in improving the channel carriers supply.
Currently, forming the structure on a p-type Si substrate for n-channel MOSFET is much moredifficult as compared to p-channel device with n-substrate, because silicidesand metals that yieldhuge barrier heights on p-type silicon are less common.
The main drawbacks of Schottkysourceldrain are high series resistance due to higher drain leakage current and finite barrier height.

Silicon on insulator & thin film transistor

Introduction:  Herein this article, the SOI and thin-film transistor (TFT) will be described in the following way.

SOI:  In contrast to thin-film transistor, top silicon layer of an SOI (silicon-on-insulator) wafer is a premium-quality single-crystalline material i.e. apt for high-density and high-performance integrated
Several forms of SOI structures have been demonstrated using different holding substrates and insulator materials.

These consist of silicon-on-oxide, silicon-on-sapphire (SOS), silicon-on-zirconia (SOZ), and siliconon-nothing(air gap). In SOZ and SOS technologies, upon a crystalline insulating substrate, single-crystalline silicon film is epitaxially grown. In these, insulators themselves serve as the substrates, ZrO₂ in SOZ and Al₂O₃ in SOS.

The difficultywith these techniques is that the material quality gets disturbed when the film gets thinner. The most popular is the one that was the first option and which used oxide as an insulator and another that used Si wafer as the holding substrate. There are several ways to construct this structure. One is where SIMOX (separation by oxygen implantation) is used and where high-dose oxygen is implanted onto a silicon wafer followed by annealing at high temeparture to create buried SiO₂ layer.

In another technique, bonding of two silicon wafers is involved. One silicon wafer has an oxidized layer followed by thinning or completely removed majority of the top wafer until a thin silicon layer is left. In one technique, lateral epitaxial growth of silicon over an oxide layer is usedthat starts from a seed opening to the substrate.

Another technique employs laser recrystallizationthat transforms amorphous silicon deposited on the oxide layer to single-crystalline material, or poly-crystalline form with large grain size. A schematic diagram of n-channel MOSFET made on an SOI substrate is shown in Figure (a) with its typical I-Vcharacteristics illustrated in Fig. (b). The kinks which are associated with floating body lacking a substrate tie are easily noticeable.

Thin-Film Transistor (TFT): The thin-film transistor is usually referred to as MOSFET unlike other types of transistors. Their structure is same as MOSFET that is built on SOI except for that their active film is a deposited thin film while it may have any form of substrate.

Since a semiconductor layer is formed by deposition, there are more defects and imperfections in amorphous material than single-crystalline semiconductors and that results in more complex transport processes in TFT. To improve the performance, reliability and reproducibility of a device, the bulk and interfacetrap densities must be diminished to reasonable levels.
Due to lower mobility, current in a TFT is always quiterestricted and leakage current is always higher because of defects.

Its main applications are in those areas where a flexible substrate or large-area is required and it is not feasible to carry out conventional semiconductor processing. Its fine example is a large-area display where an array of transistors in turn controlsan array of lighting elements.

In such applications, device performance parameters such as speed or current are not critical.