Introduction: Herein this section, the basic digital-circuit building blocks of both logic and memory circuits are presented. The basic unit for a logic circuit is an inverter. Different configurations for MOSFET inverters.
Basic Circuit Blocks:
Most commonly used is CMOS (complementary MOS) inverter where both p-channel and n-channel transistors are used. This logic uses extremely low dc power as one of the transistors in series remains off whether the input is low or high and so very little steady-state current (sub-threshold current) passes through them.
This is, in fact, one of the biggest advantages and applications of MOSFETs in which the insulated gate can tolerate input voltage of any polarity.
Such arrangement with bipolar transistors or MESFETs is quite difficult to maintain if a large resistor in not put in front of the input.
In NMOS logic (shown in Fig. b), load of p-channel transistor is substituted with a depletion-mode n-channel transistor.
The clear advantage of using this simpler technology is that it does not require a p-channel device at the expense of higher dc power.
This kind of a depletion-mode device with the gate tied to the source is a two-terminal non-linear resistor basically, which is an improvisationover a simpleresistor load that is shown in Fig. c.
Two elementary MOSFET memory cells, for DRAM (dynamic random-assess memory) and SRAM (static random-access memory) circuits, are illustrated in Fig. below.
There are two CMOS inverters connected back to back in a SRAM cell. It is a latch and a stable cell but it needs four transistors (six which includes controls for word line and bit line).
The memory density of DRAM cell is very high as it just uses one transistor. The memory is stored as a charge across its capacitor. As there is finite charge leakage in the non-ideal capacitor, the cell requiresperiodic refreshing, typically at a frequency of 100 Hz.