Power MOSFETS - DMOS & LDMOS

Introduction: Generally, power MOSFETs having longer channel lengths employ deeper junctions and thicker oxides. This also posts a penalty on device performance like the transconductance (g_m) and speed ( f_T). Yet, power applications from MOSFETs are on a rise, thanks to requirement of very high voltage, for instance, by cellular phones and cellular base stations which are in high demand.

DMOS: As implied, in DMOS (double-diffbsed MOS) transistor illustrated in Fig. (a), the higher diffusion rate of p-dopant (e.g., boron) against the n⁺-dopant (e.g., phosphorus) of the source helps in determining the channel length. This technique is capable of producing very short channels and do not depend on lithographic mask.

The p-diffusion has good punch-through control and serves as channel doping. A lightly doped n^- - drift region follows this channel. This drift region is relatively long compared to the channel and also minimizes the highest electric field in this region by maintaining a uniform field. The drain is usually located at the substrate contact.

The field near the drain is and the drift region is same and thus, avalanche breakdown, multiplication and oxide charging are diminishedin comparison to conventional MOSFETs. However, it is pretty much difficult to control the threshold voltage VT in a DMOS transistor as channel doping is not constant along its length.

As VT is determined by local doping concentration along the surface of the semiconductor, varying doping level results in variations in VT as a function of bias and distance.
Besides, the localization of punch-through control by a thin p-shield region requires a higher doping level in comparison to a conventional structure and it results in much poor turn-off behavior for DMOS transistors.



LDMOS:  The main difference between LDMOS (laterally diffused MOS) transistor (shown in Fig. b) and a DMOS transistor is that it has a lateral current-flow pattern. Herein this, the drift region is an implanted horizontal region.

This type of horizontal arrangement renders p⁺-substrate with the ability to deplete this drift region at high drain bias. Nevertheless, at low drain bias, it’s higher doping creates lower series resistance.
Thus, the drift region behaves as a nonlinear resistor. At low drain bias, its resistance is determined using 1/nqµ. At high drain bias, this region is fdly depleted to support a large voltage drop.
This concept is known as RESURF (reduced surface field) technology.

Due to this feature, drift region can be doped with much higher concentration than DMOS transistor for a lower on-resistance. The other advantage of LDMOS transistor is that source can be internally tied to the substrate with help of deep p-type diffusion.This prevents the use of a bond wire with high inductance to the source.

Thus, LDMOS transistor can perform at higher speed.